We are now going to build the mask layout view of our cmos inverter. Since we intend to use these standard cells with the automatic place and route, it is important to remember that vias must be at the intersections of the routing grid. If you have not already, please familiarize yourself with the routing grid here. For your first layout we will give you the coordinates of the design, but for future standard cells it might be helpful to build a the routing grid using text rectangles to guide the layout process. A Create New File form pops up. Cell " inv " with " layout " view will be opened in your library for you to edit.
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Please see our tutorial on setting up the design environment and running Virtuoso. This window allows you to browse the available libraries and create your own. We will create a layout view of the NAND2 cell.
Simply NAND2 should be filled in for cell-name and change the view to "layout" under view. Click OK or hit "Enter". Note that the "Application" is automatically set to "Layout XL", the layout editor. This will open two windows The first is the schematic window you just closed, and the second is the layout window below.
The layout window will be empty. NOTE unlike the schematic window, the layout window does have and use coordinates for physical positions. You want to build your layout at the origin to simplify the use of the cell by place and route tools later.
For the CDK 1. Therefore the transistors need to be mapped. Now you must set the physical library and physical cell name for each transistor. You now have two choices. You can create drag and drop instances of transistor "P-Cells" into your schematic "by hand", or you can let Virtuoso XL find the cells in the schematic and put them in the layout for you.
In either case you must first perform the mapping of logical to physical cells. That means it can directly generate the basic components into the layout for you, and it maintains connectivity information between the two views. This is not essential since we always verify that the layout is correct using the LVS verification path as well. The defaults should be set for you, as below:. Now you need to move the cells into position and wire them up. Note that when you move the cells orange "flylines" will appear telling you what should be connected to what, based on the connectivity in the schematic.
Also the pins for vdd, gnd, A and B have already been created. Other than that, the process of wiring up the cell is pretty much the same as below. Now you are ready to draw objects in the Virtuoso window. In this section you learn to place copies of other cells: pmos and nmos. These cells are parameterized cells or p-cells which change their features when you change their parameters. This will pull up the "Create Instance" dialog box. Click "close" on the browser window. Then scroll down in the create-instance dialog to look for a parameter called Width.
Make sure this is set to the same value as in you schematics e. Next, move the cursor into the layout editor window. You should see a small instance at the tip of your cursor, as shown below. You may want to zoom in before placing the instance. To do that, right-click and drag a box around the origin. When you release the button, you should see that the instance is much larger. Finally, hit "Escape" to stop adding instances. Now, you will notice that you don't immediately see what is inside the nmos symbol.
You can fix this by hitting Shift-F to display all levels of hierarchy. You may want to adjust your view so that it looks nicer. To zoom in, right-click and drag a box around the area you want to zoom in. Now, look now at the LSW Layer selection window. This window shows you the names of the layers that are "valid" meaning that you can manipulate them. You can figure out which layers are part of the NMOS cell by making them visible and in-visible.
You can make all layers visible with the "AV" button, and no layers visible with the "NV" button. Note that even if you make all layers invisible, you may still see some shapes. This is because not all layers are "valid". Shapes in invalid layers cannot be altered and are always visible. In general, it is recommended that you not set all layers as valid, because this clutters up the LSW with many unused layers.
Using this approach, you should be able to figure out that the NMOS uses the following layers: nactive , nselect , poly , metal1 , and cc contact cut. The PMOS is like it, except that it uses layers pselect and nwell instead of pwell and nimplant. Note that there is nothing magical about the p-cells. You could paint these shapes manually in the current cell-view, and it would make no difference whatsoever to the tool. Note also the letters "drw", "net", and "pin" next to each entry in the LSW.
These are the purposes of a shape. The purpose is used to indicate special functionality of a shape. We will discuss these more in later tutorials.
For now, remember that "drawing" is the purpose that indicates that a shape will appear in the mask layout. You will sometimes see "drawing" abbreviated as "drw", and sometimes "dg". By default, if you simply drag out a region while holding down the left mouse button Button-1 , whatever is within the box will be selected and highlighted in white.
Once you have selected an object that is, an instance or a shape you can do lots of things with it. The DRC form appears, as shown below. Then click "OK". If you do not see the window appear, or if you get an error, then it's possible that you didn't set up your environment in the correct order.
These are part of virtuoso and should be set up correctly for you. You will see a bunch of text scrolling through the log window. NOTE, even though most of the information in the log window is boring, it often has key information about what Virtuoso is doing, so it is very useful to keep this window open and read the messages there.
The screen should zoom to the error and the explain error box should show you the corresponding error. In our case, these match with the explanations in our text book, and on the MOSIS pages for this process. In this particular case, the transistor wells are too close together.
Fix this error by moving up the pmos. Later on you will see that we do not always want to put them as close as possible. You can draw temporary rulers by hitting "k" and dragging a ruler. You can clear the rulers by hitting "Shift-K". These rulers can help you to draw dense layout much faster than you would by constantly running DRC. Open the schematic window. Now with both windows open, click on the transistors in the schematic window. Similarly, if you click on the transistors in the layout window the transistors in the schematic will be highlighted.
As we add nets and net names, more correspondences will be tracked. We have put the upper nmos transistor to the right of the lower one, this is because we will be taking the output of the gate from the right side of the layout. Before we get started wiring up the schematic note that we are really just creating the fabrication masks for the creation of the final chip.
This means, among other things, that it usually does not matter how you create the shapes in the layout, and it usually does not matter if the shapes of the same material overlap - creating "redundant material. So, you will see some tutorials use "painting rectangles" while others use "wiring tools" and others use "path editing tools" all to achieve the same ends.
There are advantages to each, but they all work. We are now going to "paint" a piece of poly to connect the pmos and nmos devices together. We do this by creating a shape, in this case, a rectangle. You can do the same thing with the PATH command. The path command is a little different in that it knows what the minimum size for each layer is, and gives you a way to draw in that minimum size.
Also you can add bends with the tool. Finally, paths can be stretched more ways than rectangles. Now select metal 1 on the LSW pallet and then create a path for the output of the circuit. Note the contacts for each transistor already have metal1 as part of the contact structure.
We then need to connect the rails to the source nodes of the transistors. Create these rails now, and make your design look like the one below. Again, try to make the layout as compact as possible but make the supply rails double the minimum width for metal1, running DRC as often as needed to learn the design rules. If you get confused about which transistor is which, use the XL schematics window to see what should be connected to what. NOTE in this figure I also changed the transistor sizes from nm to nm to match the schematic.
This can be done by opening the object properties pop-up. Next, we need to add contacts to wells, which serve as the bulk node of the transistors. Typically people use the words Via and Contact Cut interchangeably.
Using the Virtuoso Layout Editor
Tutorial 4: Layout Generation and Editing with Layout XL